The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Application No. 99-26853 filed on Jul. 5, 1999, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a redundancy circuit which adopts a latch cell.
2. Description of the Related Art
Recently, with the development of refining techniques, semiconductor devices have become faster and more highly integrated. In particular, semiconductor memory devices require high yield together with high integration.
Semiconductor memory devices are comprised of many memory cells. However, even if one of the memory cells is defective, the semiconductor memory device no longer operates properly. With an increase in the integration of semiconductor memory devices, the possibility that defects may be generated in memory cells increases. Such defective memory cells deteriorates the function of a semiconductor memory device, thus becoming one of the main factors in lowering the yield of semiconductor memory devices. Therefore, a technique for installing a redundancy circuit for improving yield by replacing a defective cell with a redundant cell is widely used.
Generally, the redundancy circuit drives spare redundancy memory cell blocks arranged in columns and rows, and selects a redundant memory cell in the redundancy memory cell block to replace the defective cell. A method of replacing defective columns or rows including defective cells with redundant columns or rows within a redundancy memory cell block is typically used as a method of replacing defective cells. That is, if an address signal addressing a defective cell is input to the redundancy circuit, a fuse connected to a defective column and/or row is cut, so that a redundant column and/or row within the redundancy memory cell block is selected instead of the defective column and/or row.
However, in this method of using a redundancy memory cell block, when one defective cell is generated within a defective column and/or row, even the remaining non-defective cells connected to the defective column and/or row are replaced with redundancy cells within a redundant column and/or row in order to repair one defective cell. The unnecessary use of redundant memory cells, which can be used to replace other defective cells, even with a predetermined restricted redundant memory cell capacity, causes loss of redundancy efficiency. Also, when the redundancy memory cell capacity is increased to improve the redundancy efficiency, a chip is enlarged by the increasing area of a redundancy memory cell block.
Thus, a redundancy circuit for effectively repairing defective cells is required to replace the defective cells with redundant cells.
An object of the present invention is to provide a semiconductor memory device including a redundancy circuit for repairing defective cells using latch cells which are arrayed on a data line, which substantially overcomes one or more of the problems due to limitations and disadvantages of the related art.
Accordingly, to achieve the above objects, the present invention provides a semiconductor memory device in which data of memory cells arrayed in columns and rows in each memory block is input to or output from data lines, wherein when the selected memory cells are defective, latch cells are included on the data lines to replace the defective cells in response to the addresses of the defective cells.
In an embodiment, the semiconductor memory device includes a row decoder, a sub word line driver, latch cells, fuse boxes, a latch cell control unit, and a switch unit. The row decoder decodes a row address and generates a word line enable signal for selecting the word lines of a group of memory cells among the memory cells. The sub word line driver is connected to the word line enable signal, and selects a single memory cell from the group of memory cells. The latch cells are arranged in parallel along the data lines. Each of the fuse boxes has a plurality of fuses which are programmed corresponding to the addresses of defective memory cells. The latch cell control unit generates a plurality of latch cell selection signals in response to the output signal of each of the fuse boxes, and selects latch cells. The switch units connect the selected latch cells to the data lines in response to the latch cell selection signal. In the semiconductor memory device, at least two latch cells connected in parallel to each other along each of the data lines replace the defective cells using at least one fuse box.
As described above, a defective cell is replaced by a latch cell that is included in a redundancy unit, so that loss of redundancy efficiency is prevented. Also, a semiconductor memory device according to the present invention does not require a conventional redundancy memory cell block, so that the size of a chip is reduced.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.